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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 iso773x high speed, robust emc reinforced triple-channel digital isolators 1 1 features 1 ? signaling rate: up to 100 mbps ? wide supply range: 2.25 v to 5.5 v ? 2.25-v to 5.5-v level translation ? default output high and low options ? wide temperature range: ? 55 c to +125 c ? low power consumption, typical 1.5 ma per channel at 1 mbps ? low propagation delay: 11 ns typical (5-v supplies) ? high cmti: 100 kv/ s typical ? robust electromagnetic compatibility (emc) ? system-level esd, eft, and surge immunity ? low emissions ? isolation barrier life: > 40 years ? wide-soic (dw-16) and qsop (dbq-16) package options ? safety and regulatory approvals: ? reinforced insulation per din v vde v 0884- 10 (vde v 0884-10):2006-12 ? 5000 v rms (dw) and 2500 v rms (dbq) isolation rating per ul 1577 ? csa component acceptance notice 5a, iec 60950-1, iec 60601-1 and iec 61010-1 end equipment standards ? cqc certification per gb4943.1-2011 ? tuv certification according to en 60950-1 and en 61010-1 ? vde, ul, and tuv certifications for dw package complete; all other certifications are planned 2 applications industrial automation, motor control, power supplies, solar inverters, medical equipment, hybrid electric vehicles 3 description the iso773x devices are high-performance, triple- channel digital isolators with 5000 v rms (dw package) and 2500 v rms (dbq package) isolation ratings per ul 1577. this family of devices has reinforced insulation ratings according to vde, csa, tuv and cqc. the iso773x family of devices provides high electromagnetic immunity and low emissions at low power consumption, while isolating cmos or lvcmos digital i/os. each isolation channel has a logic input and output buffer separated by a silicon dioxide (sio 2 ) insulation barrier. this device comes with enable pins which can be used to put the respective outputs in high impedance for multi-master driving applications and to reduce power consumption. the iso7730 device has all three channels in the same direction and the iso7731 device has two forward and one reverse-direction channel. if the input power or signal is lost, the default output is high for devices without suffix f and low for devices with suffix f. see the device functional modes section for further details. used in conjunction with isolated power supplies, this device helps prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. through innovative chip design and layout techniques, electromagnetic compatibility of the iso773x device has been significantly enhanced to ease system-level esd, eft, surge, and emissions compliance. the iso773x family of devices is available in 16-pin wide-soic and qsop packages. device information (1) part number package body size (nom) iso7730 iso7731 soic (dw) 10.30 mm 7.50 mm ssop (dbq) 4.90 mm 3.90 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. simplified schematic v cci and gndi are supply and ground connections, respectively, for the input channels. v cco and gndo are supply and ground connections, respectively, for the output channels. outx gndo gndi inx v cco v cci isolation capacitor enx copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 power ratings ........................................................... 5 6.6 insulation specifications ............................................ 5 6.7 regulatory information .............................................. 6 6.8 safety limiting values .............................................. 6 6.9 electrical characteristics ? 5-v supply ..................... 7 6.10 supply current characteristics ? 5-v supply .......... 7 6.11 electrical characteristics ? 3.3-v supply ................ 8 6.12 supply current characteristics ? 3.3-v supply ....... 8 6.13 electrical characteristics ? 2.5-v supply ................ 9 6.14 supply current characteristics ? 2.5-v supply ....... 9 6.15 switching characteristics ? 5-v supply ................. 10 6.16 switching characteristics ? 3.3-v supply .............. 11 6.17 switching characteristics ? 2.5-v supply .............. 11 6.18 safety and insulation characteristics curves ....... 12 6.19 typical characteristics .......................................... 13 7 parameter measurement information ................ 15 8 detailed description ............................................ 17 8.1 overview ................................................................. 17 8.2 functional block diagram ....................................... 17 8.3 feature description ................................................. 18 8.4 device functional modes ........................................ 19 9 application and implementation ........................ 20 9.1 application information ............................................ 20 9.2 typical application ................................................. 20 10 power supply recommendations ..................... 23 11 layout ................................................................... 24 11.1 layout guidelines ................................................. 24 11.2 layout example .................................................... 24 12 device and documentation support ................. 25 12.1 documentation support ........................................ 25 12.2 related links ........................................................ 25 12.3 receiving notification of documentation updates 25 12.4 community resources .......................................... 25 12.5 trademarks ........................................................... 25 12.6 electrostatic discharge caution ............................ 25 12.7 glossary ................................................................ 25 13 mechanical, packaging, and orderable information ........................................................... 26 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision a (september 2016) to revision b page ? changed feature from: " vde and ul certifications... " to: " vde, ul, and tuv certifications... " ....................................... 1 ? changed the unit value of clr and cpg from: m to: mm in insulation specifications .................................................... 5 ? changed from: " according to vde and ul;... " to: " according to vde, ul, and tuv;... " in the conditions statement of regulatory information ....................................................................................................................................................... 6 ? changed from: " plan to certify " to: " certified " in column tuv of regulatory information ................................................... 6 ? changed from: " certification planned " to: " certification planned ' to ' client id number: 77311 " in column tuv of regulatory information .......................................................................................................................................................... 6 changes from original (september 2016) to revision a page ? changed v i(hys) min value from: 0.1 v cco to: 0.1 v cci in electrical characteristics ? 5-v supply ................................ 7 ? changed v i(hys) min value from: 0.1 v cco to: 0.1 v cci in electrical characteristics ? 3.3-v supply ............................. 8 ? changed v i(hys) min value from: 0.1 v cco to: 0.1 v cci in electrical characteristics ? 2.5-v supply ............................. 9 ? changed cmti min value from: 35 to: 40 in electrical characteristics ? 3.3-v supply ...................................................... 9 ? changed pwd max value from: 4.7 to: 4.9 in switching characteristics ? 5-v supply .................................................... 10 ? changed t sk(o) max value from: 3.5 to: 4 in switching characteristics ? 5-v supply ......................................................... 10 ? changed t do max value from: 9 to: 0.3 in switching characteristics ? 5-v supply ........................................................... 10 ? changed t do max value from: 9 to: 0.3 in switching characteristics ? 3.3-v supply ........................................................ 11 ? changed t do max value from: 9 to: 0.3 in switching characteristics ? 2.5-v supply ........................................................ 11 ? added note b to figure 15 ................................................................................................................................................... 16
3 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions iso7730 dw and dbq packages 16-pin soic-wb and qsop top view iso7731 dw and dbq packages 16-pin soic-wb and qsop top view pin functions pin i/o description name no. iso7730 iso7731 v cc1 1 1 ? power supply, v cc1 v cc2 16 16 ? power supply, v cc2 ina 3 3 i input, channel a inb 4 4 i input, channel b inc 5 12 i input, channel c outa 14 14 o output, channel a outb 13 13 o output, channel b outc 12 5 o output, channel c en1 ? 7 i output enable 1. output pins on side 1 are enabled when en1 is high or open and in high-impedance state when en1 is low. en2 10 10 i output enable 2. output pins on side 2 are enabled when en2 is high or open and in high-impedance state when en2 is low. nc 6, 7, 11 6, 11 ? not connected gnd1 2, 8 2, 8 ? ground connection for v cc1 gnd2 9, 15 9, 15 ? ground connection for v cc2 isolation gnd1 gnd2 9 8 en1 en2 10 7 nc nc 11 6 outc inc 12 5 inb outb 13 4 ina outa 14 3 gnd1 gnd2 15 2 v cc1 v cc2 16 1 isolation gnd1 gnd2 9 8 nc en2 10 7 nc nc 11 6 inc outc 12 5 inb outb 13 4 ina outa 14 3 gnd1 gnd2 15 2 v cc1 v cc2 16 1
4 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values except differential i/o bus voltages are with respect to the local ground terminal (gnd1 or gnd2) and are peak voltage values. (3) maximum voltage must not exceed 6 v. 6 specifications 6.1 absolute maximum ratings (1) min max unit v cc1 , v cc2 supply voltage (2) ? 0.5 6 v v voltage at inx, outx, enx ? 0.5 v ccx + 0.5 (3) v i o output current ? 15 15 ma t j junction temperature 150 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 6000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 1500 (1) v cci = input-side v cc ; v cco = output-side v cc . 6.3 recommended operating conditions min nom max unit v cc1 , v cc2 supply voltage 2.25 5.5 v v cc(uvlo+) uvlo threshold when supply voltage is rising 2 2.25 v v cc(uvlo-) uvlo threshold when supply voltage is falling 1.7 1.8 v v hys(uvlo) supply voltage uvlo hysteresis 100 200 mv i oh high-level output current v cco (1) = 5 v ? 4 ma v cco = 3.3 v ? 2 v cco = 2.5 v ? 1 i ol low-level output current v cco = 5 v 4 ma v cco = 3.3 v 2 v cco = 2.5 v 1 v ih high-level input voltage 0.7 v cci (1) v cci v v il low-level input voltage 0 0.3 v cci v dr data rate 0 100 mbps t a ambient temperature ? 55 25 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) iso773x unit dw (soic) dbq (qsop) 16 pins 16 pins r ja junction-to-ambient thermal resistance 81.4 109.0 c/w r jc(top) junction-to-case(top) thermal resistance 44.9 46.8 c/w r jb junction-to-board thermal resistance 45.9 60.6 c/w jt junction-to-top characterization parameter 28.1 35.9 c/w jb junction-to-board characterization parameter 45.5 60.0 c/w r jc(bottom) junction-to-case(bottom) thermal resistance n/a n/a c/w
5 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.5 power ratings parameter test conditions value unit iso7730 p d maximum power dissipation v cc1 = v cc2 = 5.5 v, t j = 150 c, c l = 15 pf, input a 50 mhz 50% duty cycle square wave 150 mw p d1 maximum power dissipation by side-1 25 mw p d2 maximum power dissipation by side-2 125 mw iso7731 p d maximum power dissipation v cc1 = v cc2 = 5.5 v, t j = 150 c, c l = 15 pf, input a 50 mhz 50% duty cycle square wave 150 mw p d1 maximum power dissipation by side-1 50 mw p d2 maximum power dissipation by side-2 100 mw (1) creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. (2) this coupler is suitable for safe electrical insulatio n only within the safety ratings. compliance with the safety ratings shall be ensured by means of suitable protective circuits. (3) testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (4) apparent charge is electrical discharge caused by a partial discharge (pd). (5) all pins on each side of the barrier tied together creating a two-terminal device. 6.6 insulation specifications parameter test conditions specification unit dw-16 dbq-16 clr external clearance (1) shortest terminal-to-terminal distance through air > 8 > 3.7 mm cpg external creepage (1) shortest terminal-to-terminal distance across the package surface > 8 > 3.7 mm dti distance through the insulation minimum internal gap (internal clearance) > 21 > 21 m cti comparative tracking index din en 60112 (vde 0303-11); iec 60112; ul 746a > 600 > 600 v material group according to iec 60664-1 i i overvoltage category per iec 60664-1 rated mains voltage 150 v rms i ? iv i ? iv rated mains voltage 300 v rms i ? iv i ? iii rated mains voltage 600 v rms i ? iv n/a rated mains voltage 1000 v rms i ? iii n/a din v vde v 0884-10 (vde v 0884-10):2006-12 (2) v iorm maximum repetitive peak isolation voltage ac voltage (bipolar) 1414 566 v pk v iowm maximum isolation working voltage ac voltage; time dependent dielectric breakdown (tddb) test 1000 400 v rms dc voltage 1414 566 v dc v iotm maximum transient isolation voltage v test = v iotm t = 60 s (qualification), t = 1 s (100% production) 8000 3600 v pk v iosm maximum surge isolation voltage (3) test method per iec 60065, 1.2/50 s waveform, v test = 1.6 v iosm (qualification) 8000 4000 v pk q pd apparent charge (4) method a, after input/output safety test subgroup 2/3, v ini = v iotm , t ini = 60 s; v pd(m) = 1.2 v iorm , t m = 10 s 5 5 pc method a, after environmental tests subgroup 1, v ini = v iotm , t ini = 60 s; v pd(m) = 1.6 v iorm , t m = 10 s 5 5 method b1; at routine test (100% production) and preconditioning (type test) v ini = v iotm , t ini = 1 s; v pd(m) = 1.875 v iorm , t m = 1 s 5 5 c io barrier capacitance, input to output (5) v io = 0.4 x sin (2 ft), f = 1 mhz ~0.7 ~0.7 pf r io isolation resistance (5) v io = 500 v, t a = 25 c > 10 12 > 10 12 ? v io = 500 v, 100 c t a 125 c > 10 11 > 10 11 v io = 500 v at t s = 150 c > 10 9 > 10 9 pollution degree 2 2 ul 1577 v iso withstanding isolation voltage v test = v iso , t = 60 s (qualification), v test = 1.2 v iso , t = 1 s (100% production) 5000 2500 v rms
6 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.7 regulatory information dw package devices certified according to vde, ul, and tuv; all other certifications are planned. vde csa ul cqc tuv certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 plan to certify according to csa component acceptance notice 5a, iec 60950-1, iec 61010-1, and iec 60601-1 certified according to ul 1577 component recognition program plan to certify according to gb 4943.1-2011 certified according to en 61010-1:2010 (3rd ed) and en 60950-1:2006/a11 :2009/a1:2010/a12:2011/a2 :2013 maximum transient isolation voltage, 8000 v pk (dw-16) and 3600 v pk (dbq-16); maximum repetitive peak isolation voltage, 1414 v pk (dw-16) and 566 v pk (dbq-16); maximum surge isolation voltage, 8000 v pk (dw-16) and 4000 v pk (dbq-16) reinforced insulation per csa 61010-1-12 and iec 61010-1 3rd ed., 600 v rms (dw-16 ) maximum working voltage; dw-16: single protection, 5000 v rms ; dbq-16: single protection, 2500 v rms dw-16: reinforced insulation, altitude 5000 m, tropical climate, 400 v rms maximum working voltage; dbq-16: basic insulation, altitude 5000 m, tropical climate, 250 v rms maximum working voltage 5000 v rms reinforced insulation per en 61010- 1:2010 (3rd ed) up to working voltage of 600 v rms (dw package) reinforced insulation per csa 60950-1-07+a1+a2 and iec 60950-1 2nd ed., 800 v rms (dw-16) and 370 v rms (dbq-16) max working voltage (pollution degree 2, material group i); dw-16: 2 mopp (means of patient protection) per csa 60601-1:14 and iec 60601-1 ed. 3.1, 250 v rms (354 v pk ) max working voltage 5000 v rms reinforced insulation per en 60950- 1:2006/a11:2009/a1:2010/a 12:2011/a2:2013 up to working voltage of 800 v rms (dw package) certificate number: 40040142 certification planned file number: e181974 certification planned client id number: 77311 6.8 safety limiting values safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. a failure of the i/o can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. parameter test conditions min typ max unit dw-16 package i s safety input, output, or supply current r ja = 81.4 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c, see figure 1 279 ma r ja = 81.4 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c, see figure 1 427 r ja = 81.4 c/w, v i = 2.75 v, t j = 150 c, t a = 25 c, see figure 1 558 p s safety input, output, or total power r ja = 81.4 c/w, t j = 150 c, t a = 25 c, see figure 3 1536 mw t s maximum safety temperature 150 c dbq-16 package i s safety input, output, or supply current r ja = 109.0 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c, see figure 2 209 ma r ja = 109.0 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c, see figure 2 319 r ja = 109.0 c/w, v i = 2.75 v, t j = 150 c, t a = 25 c, see figure 2 417 p s safety input, output, or total power r ja = 109.0 c/w, t j = 150 c, t a = 25 c, see figure 4 1147 mw t s maximum safety temperature 150 c the maximum safety temperature is the maximum junction temperature specified for the device. the power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. the assumed junction-to-air thermal resistance in the thermal information is that of a device installed on a high-k test board for leaded surface mount packages. the power is the recommended maximum input voltage times the current. the junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance
7 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) v cci = input-side v cc ; v cco = output-side v cc . (2) measured from input pin to ground. 6.9 electrical characteristics ? 5-v supply v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 4 ma; see figure 13 v cco (1) ? 0.4 4.8 v v ol low-level output voltage i ol = 4 ma; see figure 13 0.2 0.4 v v it+(in) rising input voltage threshold 0.6 x v cci 0.7 x v cci v v it-(in) falling input voltage threshold 0.3 x v cci 0.4 x v cci v v i(hys) input threshold voltage hysteresis 0.1 v cci 0.2 x v cci v i ih high-level input current v ih = v cci (1) at inx or enx 10 a i il low-level input current v il = 0 v at inx or enx ? 10 a cmti common-mode transient immunity v i = v cci or 0 v, v cm = 1200 v; see figure 16 40 100 kv/ s c i input capacitance (2) v i = v cc / 2 + 0.4 sin(2 ft), f = 1 mhz, v cc = 5 v 2 pf (1) v cci = input-side v cc 6.10 supply current characteristics ? 5-v supply v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions supply curren t min typ max unit iso7730 supply current - disable en2 = 0 v; v i = v cc1 (iso7730); v i = 0 v (iso7730 with f suffix) i cc1 1 1.4 ma i cc2 0.3 0.4 ma en2 = 0 v; v i = 0 v (iso7730); v i = v cc1 (iso7730 with f suffix) i cc1 4.3 6 ma i cc2 0.3 0.4 ma supply current - dc signal en2 = v cc2 ; v i = v cc1 (iso7730); v i = 0 v (iso7730 with f suffix) i cc1 1 1.4 ma i cc2 1.6 2.5 ma en2 = v cc2 ; v i = 0 v (iso7730); v i = v cc1 (iso7730 with f suffix) i cc1 4.3 6 ma i cc2 1.8 2.7 ma supply current - ac signal en2 = v cci ; all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 2.6 3.7 ma i cc2 1.9 2.8 ma 10 mbps i cc1 2.7 3.8 ma i cc2 3.3 4.5 ma 100 mbps i cc1 3.6 4.6 ma i cc2 17.5 21 ma iso7731 supply current - disable en1 = en2 = 0 v; v i = v cci (1) (iso7731); v i = 0 v (iso7731 with f suffix) i cc1 0.8 1.2 ma i cc2 0.7 1 ma en1 = en2 = 0 v; v i = 0 v (iso7731); v i = v cci (iso7731 with f suffix) i cc1 3 4.3 ma i cc2 1.8 2.6 ma supply current - dc signal en1 = en2 = v cci ; v i = v cci (iso7731); v i = 0 v (iso7731 with f suffix) i cc1 1.3 1.7 ma i cc2 1.6 2.2 ma en1 = en2 = v cci ; v i = 0 v (iso7731); v i = v cci (iso7731 with f suffix) i cc1 3.5 5 ma i cc2 2.8 4.1 ma supply current - ac signal en1 = en2 = v cci ; all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 2.7 3.4 ma i cc2 2.3 3.3 ma 10 mbps i cc1 3 4 ma i cc2 3.3 4.4 ma 100 mbps i cc1 8.5 11 ma i cc2 13.1 16 ma
8 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) v cci = input-side v cc ; v cco = output-side v cc . 6.11 electrical characteristics ? 3.3-v supply v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 2 ma; see figure 13 v cco (1) ? 0.3 3.2 v v ol low-level output voltage i ol = 2 ma; see figure 13 0.1 0.3 v v it+(in) rising input voltage threshold 0.6 x v cci 0.7 x v cci v v it-(in) falling input voltage threshold 0.3 x v cci 0.4 x v cci v v i(hys) input threshold voltage hysteresis 0.1 v cci 0.2 x v cci v i ih high-level input current v ih = v cci (1) at inx or enx 10 a i il low-level input current v il = 0 v at inx or enx ? 10 a cmti common-mode transient immunity v i = v cci or 0 v, v cm = 1200 v; see figure 16 40 100 kv/ s (1) v cci = input-side v cc 6.12 supply current characteristics ? 3.3-v supply v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions supply current min typ max unit iso7730 supply current - disable en2 = 0 v; v i = v cc1 (iso7730); v i = 0 v (iso7730 with f suffix) i cc1 1 1.4 ma i cc2 0.3 0.4 ma en2 = 0 v; v i = 0 v (iso7730); v i = v cc1 (iso7730 with f suffix) i cc1 4.3 6 ma i cc2 0.3 0.4 ma supply current - dc signal en2 = v cc2 ; v i = v cc1 (iso7730); v i = 0 v (iso7730 with f suffix) i cc1 1 1.4 ma i cc2 1.6 2.5 ma en2 = v cc2 ; v i = 0 v (iso7730); v i = v cc1 (iso7730 with f suffix) i cc1 4.3 6 ma i cc2 1.8 2.7 ma supply current - ac signal en2 = v cci ; all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 2.6 3.7 ma i cc2 1.8 2.8 ma 10 mbps i cc1 2.7 3.8 ma i cc2 2.8 3.9 ma 100 mbps i cc1 3.3 4.3 ma i cc2 13 17 ma iso7731 supply current - disable en1 = en2 = 0 v; v i = v cci (1) (iso7731); v i = 0 v (iso7731 with f suffix) i cc1 0.8 1.2 ma i cc2 0.7 1 ma en1 = en2 = 0 v; v i = 0 v (iso7731); v i = v cci (iso7731 with f suffix) i cc1 3 4.3 ma i cc2 1.8 2.6 ma supply current - dc signal en1 = en2 = v cci ; v i = v cci (iso7731); v i = 0 v (iso7731 with f suffix) i cc1 1.3 1.7 ma i cc2 1.6 2.2 ma en1 = en2 = v cci ; v i = 0 v (iso7731); v i = v cci (iso7731 with f suffix) i cc1 3.5 5 ma i cc2 2.8 4.1 ma supply current - ac signal en1 = en2 = v cci ; all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 2.4 3.4 ma i cc2 2.2 3.3 ma 10 mbps i cc1 2.8 3.8 ma i cc2 2.9 4 ma 100 mbps i cc1 6.7 8.5 ma i cc2 10 12.5 ma
9 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) v cci = input-side v cc ; v cco = output-side v cc . 6.13 electrical characteristics ? 2.5-v supply v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 1 ma; see figure 13 v cco (1) ? 0.2 2.45 v v ol low-level output voltage i ol = 1 ma; see figure 13 0.05 0.2 v v it+(in) rising input voltage threshold 0.6 x v cci 0.7 x v cci v v it-(in) falling input voltage threshold 0.3 x v cci 0.4 x v cci v v i(hys) input threshold voltage hysteresis 0.1 v cci 0.2 x v cci v i ih high-level input current v ih = v cci (1) at inx or enx 10 a i il low-level input current v il = 0 v at inx or enx ? 10 a cmti common-mode transient immunity v i = v cci or 0 v, v cm = 1200 v; see figure 16 40 100 kv/ s (1) v cci = input-side v cc 6.14 supply current characteristics ? 2.5-v supply v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions supply current min typ max unit iso7730 supply current - disable en2 = 0 v; v i = v cc1 (iso7730); v i = 0 v (iso7730 with f suffix) i cc1 1 1.4 ma i cc2 0.3 0.4 ma en2 = 0 v; v i = 0 v (iso7730); v i = v cc1 (iso7730 with f suffix) i cc1 4.3 6 ma i cc2 0.3 0.4 ma supply current - dc signal en2 = v cc2 ; v i = v cc1 (iso7730); v i = 0 v (iso7730 with f suffix) i cc1 1 1.4 ma i cc2 1.6 2.5 ma en2 = v cc2 ; v i = 0 v (iso7730); v i = v cc1 (iso7730 with f suffix) i cc1 4.3 6 ma i cc2 1.8 2.7 ma supply current - ac signal en2 = v cc2 ; all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 2.6 3.7 ma i cc2 1.8 2.7 ma 10 mbps i cc1 2.6 3.8 ma i cc2 2.5 3.6 ma 100 mbps i cc1 3.1 4.2 ma i cc2 10.2 14 ma iso7731 supply current - disable en1 = en2 = 0 v; v i = v cci (1) (iso7731); v i = 0 v (iso7731 with f suffix) i cc1 0.8 1.2 ma i cc2 0.7 1 ma en1 = en2 = 0 v; v i = 0 v (iso7731); v i = v cci (iso7731 with f suffix) i cc1 3 4.3 ma i cc2 1.8 2.6 ma supply current - dc signal en1 = en2 = v cci ; v i = v cci (iso7731); v i = 0 v (iso7731 with f suffix) i cc1 1.3 1.7 ma i cc2 1.6 2.2 ma en1 = en2 = v cci ; v i = 0 v (iso7731); v i = v cci (iso7731 with f suffix) i cc1 3.5 5 ma i cc2 2.8 4.1 ma supply current - ac signal en1 = en2 = v cci ; all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 2.4 3.4 ma i cc2 2.2 3.2 ma 10 mbps i cc1 2.7 3.7 ma i cc2 2.7 3.8 ma 100 mbps i cc1 5.6 7 ma i cc2 8 10 ma
10 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.15 switching characteristics ? 5-v supply v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 13 6 11 16 ns pwd pulse width distortion (1) |t phl ? t plh | 0.6 4.9 ns t sk(o) channel-to-channel output skew time (2) same-direction channels 4 ns t sk(pp) part-to-part skew time (3) 4.5 ns t r output signal rise time see figure 13 1.3 3.9 ns t f output signal fall time 1.4 3.9 ns t phz disable propagation delay, high-to-high impedance output see figure 14 8 20 ns t plz disable propagation delay, low-to-high impedance output 8 20 ns t pzh enable propagation delay, high impedance-to-high output for iso773x 7 20 ns enable propagation delay, high impedance-to-high output for iso773x with f suffix 3 8.5 s t pzl enable propagation delay, high impedance-to-low output for iso773x 3 8.5 s enable propagation delay, high impedance-to-low output for iso773x with f suffix 7 20 ns t do default output delay time from input power loss measured from the time v cc goes below 1.7 v. see figure 15 0.1 0.3 s t ie time interval error 2 16 ? 1 prbs data at 100 mbps 0.6 ns
11 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.16 switching characteristics ? 3.3-v supply v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 13 6 11 16 ns pwd pulse width distortion (1) |t phl ? t plh | 0.1 5 ns t sk(o) channel-to-channel output skew time (2) same-direction channels 4.1 ns t sk(pp) part-to-part skew time (3) 4.5 ns t r output signal rise time see figure 13 1.3 3 ns t f output signal fall time 1.3 3 ns t phz disable propagation delay, high-to-high impedance output see figure 14 17 30 ns t plz disable propagation delay, low-to-high impedance output 17 30 ns t pzh enable propagation delay, high impedance-to-high output for iso773x 17 30 ns enable propagation delay, high impedance-to-high output for iso773x with f suffix 3.2 8.5 s t pzl enable propagation delay, high impedance-to-low output for iso773x 3.2 8.5 s enable propagation delay, high impedance-to-low output for iso773x with f suffix 17 30 ns t do default output delay time from input power loss measured from the time v cc goes below 1.7 v. see figure 15 0.1 0.3 s t ie time interval error 2 16 ? 1 prbs data at 100 mbps 0.6 ns (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.17 switching characteristics ? 2.5-v supply v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 13 7.5 12 18.5 ns pwd pulse width distortion (1) |t phl ? t plh | 0.2 5.1 ns t sk(o) channel-to-channel output skew time (2) same-direction channels 4.1 ns t sk(pp) part-to-part skew time (3) 4.6 ns t r output signal rise time see figure 13 1 3.5 ns t f output signal fall time 1 3.5 ns t phz disable propagation delay, high-to-high impedance output see figure 14 22 40 ns t plz disable propagation delay, low-to-high impedance output 22 40 ns t pzh enable propagation delay, high impedance-to-high output for iso773x 18 40 ns enable propagation delay, high impedance-to-high output for iso773x with f suffix 3.3 8.5 s t pzl enable propagation delay, high impedance-to-low output for iso773x 3.3 8.5 s enable propagation delay, high impedance-to-low output for iso773x with f suffix 18 40 ns t do default output delay time from input power loss measured from the time v cc goes below 1.7 v. see figure 15 0.1 0.3 s t ie time interval error 2 16 ? 1 prbs data at 100 mbps 0.6 ns
12 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.18 safety and insulation characteristics curves figure 1. thermal derating curve for safety limiting current per vde for dw-16 package figure 2. thermal derating curve for safety limiting current per vde for dbq-16 package figure 3. thermal derating curve for safety limiting power per vde for dw-16 package figure 4. thermal derating curve for safety limiting power per vde for dbq-16 package ambient temperature ( q c) safety limiting current (ma) 0 50 100 150 200 0 100 200 300 400 500 600 d001 v cc1 = v cc2 = 2.75 v v cc1 = v cc2 = 3.6 v v cc1 = v cc2 = 5.5 v ambient temperature ( q c) safety limiting current (ma) 0 50 100 150 200 0 50 100 150 200 250 300 350 400 450 d002 v cc1 = v cc2 = 2.75 v v cc1 = v cc2 = 3.6 v v cc1 = v cc2 = 5.5 v ambient temperature ( q c) safety limiting power (mw) 0 50 100 150 200 0 200 400 600 800 1000 1200 1400 1600 1800 d003 ambient temperature ( q c) safety limiting power (mw) 0 50 100 150 200 0 200 400 600 800 1000 1200 1400 d004
13 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.19 typical characteristics t a = 25 c c l = 15 pf figure 5. iso7730 supply current vs data rate (with 15-pf load) t a = 25 c c l = no load figure 6. iso7730 supply current vs data rate (with no load) t a = 25 c c l = 15 pf figure 7. iso7731 supply current vs data rate (with 15-pf load) t a = 25 c c l = no load figure 8. iso7731 supply current vs data rate (with no load) t a = 25 c figure 9. high-level output voltage vs high-level output current t a = 25 c figure 10. low-level output voltage vs low-level output current high-level output current (ma) high-level output voltage (v) -15 -10 -5 0 0 1 2 3 4 5 6 d011 v cc at 2.5 v v cc at 3.3 v v cc at 5 v low-level output current (ma) low-level output voltage (v) 0 5 10 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 d012 v cc at 2.5 v v cc at 3.3 v v cc at 5 v data rate (mbps) supply current (ma) 0 25 50 75 100 0 2 4 6 8 10 12 14 d007 icc1 at 2.5 v icc2 at 2.5 v icc1 at 3.3 v icc2 at 3.3 v icc1 at 5 v icc2 at 5 v data rate (mbps) supply current (ma) 0 25 50 75 100 0 1 2 3 4 5 6 d008 icc1 at 2.5 v icc2 at 2.5 v icc1 at 3.3 v icc2 at 3.3 v icc1 at 5 v icc2 at 5 v data rate (mbps) supply current (ma) 0 25 50 75 100 0 2 4 6 8 10 12 14 16 18 20 d005 icc1 at 2.5 v icc2 at 2.5 v icc1 at 3.3 v icc2 at 3.3 v icc1 at 5 v icc2 at 5 v data rate (mbps) supply current (ma) 1 26 51 76 100 1 2 3 4 5 6 7 d006 icc1 at 2.5 v icc2 at 2.5 v icc1 at 3.3 v icc2 at 3.3 v icc1 at 5 v icc2 at 5 v
14 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 11. power supply undervoltage threshold vs free-air temperature figure 12. propagation delay time vs free-air temperature free-air temperature ( q c) propagation delay time (ns) -55 -25 5 35 65 95 125 8 9 10 11 12 13 14 d010 t plh at 2.5 v t phl at 2.5 v t plh at 3.3 v t phl at 3.3 v t plh at 5 v t phl at 5 v free-air temperature ( q c) power supply uvlo threshold (v) -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 d009 vcc1 rising vcc1 falling vcc2 rising vcc2 falling
15 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 7 parameter measurement information a. the input pulse is supplied by a generator having the following characteristics: prr 50 khz, 50% duty cycle, t r 3 ns, t f 3ns, z o = 50 . at the input, 50 resistor is required to terminate input generator signal. it is not needed in actual application. b. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 13. switching characteristics test circuit and voltage waveforms a. the input pulse is supplied by a generator having the following characteristics: prr 10 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 . b. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 14. enable/disable propagation delay time test circuit and waveform in out c l see note b v o v i v ol v oh v cci 0 v t r isolation barrier 50 input generator (see note a) v i v o t f t plh t phl 50% 50% 50% 50% 90% 10% copyright ? 2016, texas instruments incorporated input generator (see note a) input generator (see note a) in out isolation barrier in out isolation barrier v o v o c l see note b c l see note b 50 50 0 v 3 v en en v cco r l = 1 k 1% r l = 1 k 1% v i v i v o v i t pzl v cc / 2 50% v cc v cc / 2 v oh 0 v v ol t plz 0.5 v v o v i t pzh v cc / 2 50% v cc v cc / 2 v oh 0 v 0 v t phz 0.5 v copyright ? 2016, texas instruments incorporated
16 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated parameter measurement information (continued) a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. b. power supply ramp rate = 10 mv/ns figure 15. default output delay time test circuit and voltage waveforms a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 16. common-mode transient immunity test circuit in out isolation barrier en v cco c l see note a s1 gndo gndi + v cm + v oh or v ol c = 0.1 f 1% c = 0.1 f 1% v cci pass-fail criteria: the output must remain stable. copyright ? 2016, texas instruments incorporated v i v cc in out v o c l see note a in = 0 v (devices without suffix f) in = v cc (devices with suffix f) v o v i v ol v oh v cc 0 v 1.7 v 50% t do default high default low isolation barrier copyright ? 2016, texas instruments incorporated see note b
17 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 8 detailed description 8.1 overview the iso773x family of devices has an on-off keying (ook) modulation scheme to transmit the digital data across a silicon dioxide based isolation barrier. the transmitter sends a high frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. the receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. if the enx pin is low then the output goes to high impedance. the iso773x family of devices also incorporates advanced circuit techniques to maximize the cmti performance and minimize the radiated emissions due the high frequency carrier and io buffer switching. the conceptual block diagram of a digital capacitive isolator, figure 17 , shows a functional block diagram of a typical channel. 8.2 functional block diagram figure 17. conceptual block diagram of a digital capacitive isolator figure 18 shows a conceptual detail of how the on/off keying scheme works. figure 18. on-off keying (ook) based modulation scheme tx in rx out carrier signal through isolation barrier tx in oscillator ook modulation transmitter emissions reduction techniques tx signal conditioning envelope detection rx signal conditioning receiver en rx out sio 2 based capacitive isolation barrier copyright ? 2016, texas instruments incorporated
18 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) see regulatory information for detailed isolation ratings. 8.3 feature description table 1 provides an overview of the device features. table 1. device features part number channel direction maximum data rate default output package rated isolation (1) iso7730 3 forward, 0 reverse 100 mbps high dw-16 5000 v rms / 8000 v pk dbq-16 2500 v rms / 3600 v pk iso7730 with f suffix 3 forward, 0 reverse 100 mbps low dw-16 5000 v rms / 8000 v pk dbq-16 2500 v rms / 3600 v pk iso7731 2 forward, 1 reverse 100 mbps high dw-16 5000 v rms / 8000 v pk dbq-16 2500 v rms / 3600 v pk iso7731 with f suffix 2 forward, 1 reverse 100 mbps low dw-16 5000 v rms / 8000 v pk dbq-16 2500 v rms / 3600 v pk 8.3.1 electromagnetic compatibility (emc) considerations many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (esd), electrical fast transient (eft), surge and electromagnetic emissions. these electromagnetic disturbances are regulated by international standards such as iec 61000-4-x and cispr 22. although system-level performance and reliability depends, to a large extent, on the application board design and layout, the iso773x family of devices incorporates many chip-level design improvements for overall system robustness. some of these improvements include: ? robust esd protection cells for input and output signal pins and inter-chip bond pads. ? low-resistance connectivity of esd cells to supply and ground pins. ? enhanced performance of high voltage isolation capacitor for better tolerance of esd, eft and surge events. ? bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. ? pmos and nmos devices isolated from each other by using guard rings to avoid triggering of parasitic scrs. ? reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.
19 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) v cci = input-side v cc ; v cco = output-side v cc ; pu = powered up (v cc 2.25 v); pd = powered down (v cc 1.7 v); x = irrelevant; h = high level; l = low level ; z = high impedance (2) a strongly driven input signal can weakly power the floating v cc via an internal protection diode and cause undetermined output. (3) the outputs are in undetermined state when 1.7 v < v cci , v cco < 2.25 v. 8.4 device functional modes table 2 lists the functional modes for the iso773x devices. table 2. function table (1) v cci v cco input (inx) (2) output enable (enx) output (outx) comments pu pu h h or open h normal operation: a channel output assumes the logic state of its input. l h or open l open h or open default default mode: when inx is open, the corresponding channel output goes to its default logic state. default= high for iso773x and low for iso773x with f suffix. x pu x l z a low value of output enable causes the outputs to be high-impedance pd pu x h or open default default mode: when v cci is unpowered, a channel output assumes the logic state based on the selected default option. default= high for iso773x and low for iso773x with f suffix. when v cci transitions from unpowered to powered-up, a channel output assumes the logic state of its input. when v cci transitions from powered-up to unpowered, channel output assumes the selected default state. x pd x x undetermined when v cco is unpowered, a channel output is undetermined (3) . when v cco transitions from unpowered to powered-up, a channel output assumes the logic state of its input 8.4.1 device i/o schematics figure 19. device i/o schematics 985 1.5 m inx v cci v cci v cci input (devices without f suffix) 985 1.5 m inx v cci v cci v cci v cci input (devices with f suffix) enable 1970 2 m enx v cco v cco v cco v cco output v cco ~20 outx copyright ? 2016, texas instruments incorporated
20 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the iso773x devices are high-performance, triple-channel digital isolators. these devices come with enable pins on each side which can be used to put the respective outputs in high impedance for multi-master driving applications and reduce power consumption. the iso773x family of devices use single-ended cmos-logic switching technology. the voltage range is from 2.25 v to 5.5 v for both supplies, v cc1 and v cc2 . when designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended cmos or ttl digital signal lines. the isolator is typically placed between the data controller (that is, c or uart), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 typical application the iso7731 device, combined with texas instruments' mixed-signal microcontroller, rs-485 transceiver, transformer driver, and voltage regulator, can create an isolated rs-485 system as shown in figure 20 . figure 20. isolated rs-485 interface circuit v cc1 v cc2 gnd1 gnd2 16 13 12 2,8 9,15 uca0rxd p3.0 uca0txd 16 1115 4 xout xin 56 2 msp430 f2132 1 34 5 7 0.1 f 0.1 f iso7731 iso-barrier 4.7nf/ 2kv sm712 10 melf 0.1 f dvss dvcc 10 f 0.1 f mbr0520l mbr0520l 1:2.2 0.1 f 31 d2 sn6501 d1 vcc 4,5 2 gnd in en gnd out 1 52 3 tps76350 10 f 10 f 10 melf v in 3.3v 5v iso ina inb outc en1 outa outb inc sn65hvd 3082e re de d r en2 14 10 1 4 3 2 b a v cc gnd 0.1 f copyright ? 2016, texas instruments incorporated
21 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated typical application (continued) 9.2.1 design requirements to design with these devices, use the parameters listed in table 3 . table 3. design parameters parameter value supply voltage, v cc1 and v cc2 2.25 to 5.5 v decoupling capacitor between v cc1 and gnd1 0.1 f decoupling capacitor from v cc2 and gnd2 0.1 f 9.2.2 detailed design procedure unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the iso773x family of devices only requires two external bypass capacitors to operate. figure 21 and figure 22 show the typical circuit hook-up for the devices. figure 21. typical iso7730 circuit hook-up 12 34 5 6 7 8 16 15 14 13 12 11 10 9 ina inb outc nc outa outb inc nc gnd2 v cc2 0.1 f 2 mm max from v cc2 en gnd2 nc gnd1 2 mm max from v cc1 gnd1 0.1 f v cc1 copyright ? 2016, texas instruments incorporated
22 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated figure 22. typical iso7731 circuit hook-up 12 34 5 6 7 8 16 15 14 13 12 11 10 9 ina inb outc nc outa outb inc nc gnd2 v cc2 0.1 f 2 mm max from v cc2 en2 gnd2 en1 gnd1 2 mm max from v cc1 gnd1 0.1 f v cc1 copyright ? 2016, texas instruments incorporated
23 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 9.2.3 application curves the following typical eye diagrams of the iso773x family of devices indicate low jitter and wide open eye at the maximum data rate of 100 mbps. figure 23. eye diagram at 100 mbps prbs 2 16 - 1, 5 v and 25 c figure 24. eye diagram at 100 mbps prbs 2 16 - 1, 3.3 v and 25 c figure 25. eye diagram at 100 mbps prbs 2 16 - 1, 2.5 v and 25 c 10 power supply recommendations to help ensure reliable operation at data rates and supply voltages, a 0.1- f bypass capacitor is recommended at the input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as texas instruments' sn6501 or sn6505a . for such applications, detailed power supply design and transformer selection recommendations are available in the sn6501 data sheet ( sllsea0 ) or sn6505a data sheet ( sllsep9 ). time = 2.5 ns / div ch4 = 1 v / div time = 2.5 ns / div ch4 = 500 mv / div time = 2.5 ns / div ch4 = 1 v / div
24 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 26 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pf/inch 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. if an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, see the application note, digital isolator design guide ( slla284 ). 11.1.1 pcb material for digital circuit boards operating below 150 mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 ul94v-0 printed circuit boards. this pcb is preferred over cheaper alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and self-extinguishing flammability-characteristics. 11.2 layout example figure 26. layout example schematic 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces, pads, and vias ground plane power plane low-speed traces high-speed traces
25 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation, see the following: ? isolation glossary , slla353 ? sn6501 transformer driver for isolated power supplies , sllsea0 ? snx5hvd308xe low-power rs-485 transceivers, available in a small msop-8 package , slls562 ? tps76350 low-power 150-ma low-dropout linear regulators , slvs181 ? msp430f2132 mixed signal microcontroller , slas578 12.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 4. related links parts product folder sample & buy technical documents tools & software support & community iso7730 click here click here click here click here click here iso7731 click here click here click here click here click here 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 trademarks e2e is a trademark of texas instruments. 12.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions.
26 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
27 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated www.ti.com package outline c typ 10.639.97 2.65 max 14x 1.27 16x 0.510.31 2x 8.89 typ 0.380.25 0 - 8 0.30.1 (1.4) 0.25 gage plane 1.270.40 a note 3 10.510.1 b note 4 7.67.4 4221009/a 08/2013 soic - 2.65 mm max height dw0016b soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm, per side. 5. reference jedec registration mo-013, variation aa. 1 16 0.25 c a b 9 8 pin 1 idarea seating plane 0.1 c see detail a typical detail a scale 1.500
28 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated www.ti.com example board layout (9.75) 0.07 max all around 0.07 min all around (9.3) 14x (1.27) 16x (1.65) 16x (0.6) 14x (1.27) 16x (2) 16x (0.6) 4221009/a 08/2013 symm soic - 2.65 mm max height dw0016b soic symm see details 1 8 9 16 symm hv / isolation option 8.1 mm clearance/creepage notes: (continued) 6. publication ipc-7351 may have alternate designs.7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder maskopening non solder mask defined opening solder mask details solder mask metal solder mask defined scale:4x land pattern example symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage see details
29 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated www.ti.com example stencil design 16x (1.65) 16x (0.6) 14x (1.27) (9.75) 16x (2) 16x (0.6) 14x (1.27) (9.3) 4221009/a 08/2013 soic - 2.65 mm max height dw0016b soic notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 8 9 16 hv / isolation option 8.1 mm clearance/creepage based on 0.125 mm thick stencil solder paste example scale:4x symm symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage
30 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated www.ti.com package outline c typ -.244 .228 -6.19 5.80 [ ] .069 max [1.75] 14x .0250 [0.635] 16x -.012 .008 -0.30 0.21 [ ] 2x .175[4.45] typ -.010 .005 -0.25 0.13 [ ] 0 - 8 -.010 .004 -0.25 0.11 [ ] (.041 ) [1.04] .010[0.25] gage plane -.035 .016 -0.88 0.41 [ ] a note 3 -.197 .189 -5.00 4.81 [ ] b note 4 -.157 .150 -3.98 3.81 [ ] shrink small-outline package ssop - 1.75 mm max height dbq0016a 4214846/a 03/2014 notes: 1. linear dimensions are in inches [millimeters]. dimensions in parenthesis are for reference only. controlling dimensions are in inches. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. this dimension does not include interlead flash. 5. reference jedec registration mo-137, variation ab. 1 16 .007 [0.17] c a b 9 8 pin 1 id area seating plane .004 [0.1] c see detail a typical detail a scale 2.800
31 iso7730 , iso7731 www.ti.com sllses0b ? september 2016 ? revised october 2016 product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated www.ti.com example board layout .002 max [0.05] all around .002 min[0.05] all around (.213) [5.4] 14x (.0250 ) [0.635] 16x (.063) [1.6] 16x (.016 ) [0.41] shrink small-outline package ssop - 1.75 mm max height dbq0016a 4214846/a 03/2014 notes: (continued) 6. publication ipc-7351 may have alternate designs.7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder maskopening non solder mask defined opening solder mask details solder mask metal solder mask defined scale:8x land pattern example symm 18 9 16 see details
32 iso7730 , iso7731 sllses0b ? september 2016 ? revised october 2016 www.ti.com product folder links: iso7730 iso7731 submit documentation feedback copyright ? 2016, texas instruments incorporated www.ti.com example stencil design 16x (.063) [1.6] 16x (.016 ) [0.41] 14x (.0250 ) [0.635] (.213) [5.4] shrink small-outline package ssop - 1.75 mm max height dbq0016a 4214846/a 03/2014 notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. solder paste example based on .005 inch [0.127 mm] thick stencil scale:8x symm symm 1 8 9 16
package option addendum www.ti.com 25-oct-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ISO7730DW active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7730 ISO7730DWr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7730 iso7730fdw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7730f iso7730fdwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7730f iso7731dw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7731 iso7731dwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7731 iso7731fdw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7731f iso7731fdwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 iso7731f (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 25-oct-2016 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ISO7730DWr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 iso7730fdwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 iso7731dwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 iso7731fdwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 package materials information www.ti.com 14-oct-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ISO7730DWr soic dw 16 2000 367.0 367.0 38.0 iso7730fdwr soic dw 16 2000 367.0 367.0 38.0 iso7731dwr soic dw 16 2000 367.0 367.0 38.0 iso7731fdwr soic dw 16 2000 367.0 367.0 38.0 package materials information www.ti.com 14-oct-2016 pack materials-page 2
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